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Program & Presentations
Saturday, 4 August 2007
8:30-9:15: Registration
9:15-9:30: Welcome and Opening
9:30-10:30: Keynote: Chas. Boyd, Microsoft
Mass Market Applications of Data-Parallel Computing (slides)
Silicon fabrication processes promise an embarrassment of processor cores
arriving in the next few years. While multi-core machines can scale to small
single-digit factors, academic researchers and the new GPGPU community have
identified the data-parallel programming model as a way for applications to
scale to 1000s of cores. To date, most of the applications evaluated have
been in the technical and scientific arenas, but what about more mass-market
applications for data-parallel programming? What features of data-parallel
processors are most important to such applications? And how might such
processors and their host systems change in order to better target them in the
future?
Chas. Boyd joined the Direct3D team in 1995 and has contributed to
releases since DirectX 5. Over that time he worked closely with hardware
and software developers to drive the adoption of features like
programmable hardware shaders and float pixel processing. He has
demonstrated initial hardware accelerated versions of techniques
including hardware soft skinning, hemispheric lighting with ambient
occlusion, matrix palette skinning, and N-Patches. Earlier he worked in
the areas of scientific visualization and 3D modeling, and more recently
on games and on APIs for GPGPU computing.
10:30-11:00: Coffee Break
11:00-12:15: Papers: Rasterization and Rendering (session
chair: John Owens, UC Davis)
Stochastic Rasterization using Time-Continuous Triangles
(slides)
Tomas Akenine-Möller, Lund University; Jacob Munkberg, Lund University; Jon Hasselgren, Lund University
Practical logarithmic rasterization for low-error shadow
maps (slides)
D. Brandon Lloyd, University of North Carolina at Chapel Hill; Naga K. Govindaraju, Microsoft Corporation; Steven E. Molnar, NVIDIA Corporation; Dinesh Manocha, University of North Carolina at Chapel Hill
Accelerating Real-Time Shading with Reverse Reprojection
Caching (slides)
Diego Nehab, Princeton University; Pedro Sander, Hong Kong University of Science and Technology; Jason Lawrence, University of Virginia; Natalya Tatarchuk, Advanced Micro Devices, Inc.; John Isidoro, Advanced Micro Devices, Inc.
12:15-14:00: Lunch Break
14:00-15:15: Papers: Compression (session chair: David
McAllister, NVIDIA)
Tight Frame Normal Map Compression (slides)
Jacob Munkberg, Lund University; Ola Olsson, Lund University; Jacob Ström, Ericsson Research; Tomas Akenine-Möller, Lund University
Exact and Error-bounded Approximate Color Buffer Compression and
Decompression (slides)
Jim Rasmusson, Lund University / Ericsson Research; Jon Hasselgren, Lund University; Tomas Akenine-Möller, Lund University
ETC2: Texture Compression using Invalid Combinations (slides)
Jacob Ström, Ericsson Research; Martin Pettersson, Ericsson Research
15:15-16:00: Coffee Break
16:00-17:00: Panel: Whither graphics hardware, and Graphics
Hardware
Moderator: Mark Segal (Google)
Panelists: Marc Olano (UMBC) (slides),
David Kirk (NVIDIA) (slides), Steve Morein (AMD), Bill Mark (The University
of Texas) (slides),
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Once again, the graphics hardware landscape is changing. In
the last couple of years, we have seen, among other things, a
resurgent interest in hardware ray-tracing, lower-level and
non-graphics-centric APIs for computation on GPUs, use of GPUs
for non-graphics computation in commercial applications,
dedicated 3D graphics hardware in cell phones, and the
announcement by at least one vendor of a CPU and GPU on the
same die. In addition, the recent evolution of CPUs (namely,
multicore) promises to affect the design and application of
graphics hardware. Our panelists will discuss these trends,
and what they portend for the future.
As graphics hardware evolves, so must the Graphics Hardware
conference. Besides debating the opportunities presented by
the technology trends, the panelists will also debate and
solicit ideas from the audience on what changes might be
appropriate for Graphics Hardware to better reflect the
changing landscape and attract a wider audience.
We expect the discussion to be a lively one, with plenty of
opportunity for audience participation.
17:00-17:45: Free Time
17:45-23:00: Social Event: cruise in San Diego Bay on
the Pacific
Hornblower (directions). Extra
tickets available (under cost) at $75.
Sunday, 5 August 2007
9:00-10:00: Keynote: Michael Jones, Google
GPUs for the true mass market (slides)
The single most widely-used real-time 3D graphics application is not a
game, it is Google Earth. With more than 250 million unique users to
date, its popularity exceeds not just game titles, but entire console
gaming platforms. This mass market position is an opportunity to
introduce users worldwide to an increasingly advanced level of rendering
sophistication through exploitation of programmable graphics hardware.
In his keynote remarks, Michael will address a range of areas where
tomorrow's multi-CPU/multi-GPU ensembles could transform the power of
distributed geospatial browsing.
Michael Jones is the Chief Technologist of Google Earth, Maps, and Local
Search—Google's efforts to provide location intelligence and
information in a global context for users worldwide. Michael was
formerly the CTO of Keyhole Corporation, the company that developed the
technology used today in Google Earth. He was also CEO of Intrinsic
Graphics, and earlier, was Director of Advanced Graphics at Silicon
Graphics, where he was responsible for graphics APIs including OpenGL,
IRIS Performer, the ImageVision Library, OpenGL Optimizer, and Cosmo3D.
Michael holds 12 issued patents, including the ClipMapping technique
first seen in the SGI InfiniteReality. For many years, he has been a
developer of scientific and interactive computer graphics software, an
avid traveler, and an amateur photographer using a home-built 4
gigapixel camera made with declassified and decommissioned parts from
the U2/SR71.
10:00-10:30: Coffee Break
10:30-11:45: Papers: Architecture (session chair: Gordon
Elder, AMD)
A Hardware Redundancy and Recovery Mechanism for Reliable
Scientific Computation on Graphics Processors (slides)
Jeremy Sheaffer, University of Virginia; David Luebke, NVIDIA Research; Kevin Skadron, University of Virginia
A Real-Time FPGA-based Architecture For a Reinhard-like Tone
Mapping Operator (slides)
Firas Hassan, The University of Akron; Joan Carletta, The University of Akron
A Low-Power Handheld GPU using Logarithmic Arithmetic and
Triple DVFS Power Domains (slides)
Byeong-Gyu Nam, Korea Advanced Institute of Science and Technology (KAIST); Jeabin Lee, Korea Advanced Institute of Science and Technology (KAIST); Kwanho Kim, Korea Advanced Institute of Science and Technology (KAIST); Seung Jin Lee, Korea Advanced Institute of Science and Technology (KAIST); Hoi-Jun Yoo, Korea Advanced Institute of Science and Technology (KAIST)
11:45-13:30: Lunch Break
13:30-14:45: Papers: Programming and Algorithms (session
chair: Robert Strzodka, Stanford/MPI)
A Hardware-Aware Debugger for the OpenGL Shading
Language (slides)
Magnus Strengert, University of Stuttgart; Thomas Klein, University of Stuttgart; Thomas Ertl, University of Stuttgart
Programmable Shaders for Deformation Rendering (slides)
Carlos Correa, Rutgers University; Deborah Silver, Rutgers University
Scan Primitives for GPU Computing
(slides) Best
Paper award
Shubhabrata Sengupta, University of California, Davis; Mark
Harris, NVIDIA Corporation; Yao Zhang, University of California, Davis; John D. Owens, University of California, Davis
14:45-15:15: Coffee Break
15:15-16:15: Hot3D session (chair: Peter Glaskowsky)
John Nickolls, Lead Architect, NVIDIA Compute. NVIDIA Tesla
and the GPU Parallel Computing Architecture (slides)
The talk will describe NVIDIA's new Tesla GPU Computing processor
architecture and hardware for high performance parallel computing.
The Tesla C870 is a massively multithreaded architecture with 128
processor cores and over 500 GFLOPS peak floating point performance.
It is programmable in C with the CUDA software development
environment.
John Nickolls is director of architecture at NVIDIA for GPU computing.
He was previously at Broadcom, Silicon Spice, Sun, and was a
co-founder of MasPar Computer. His interests include parallel systems
and parallel processor architecture. Nickolls has a BS in electrical
engineering and computer science from the University of Illinois, and
MS and PhD degrees in electrical engineering from Stanford University. Michael Doggett, AMD. AMD's Radeon HD 2900 (slides)
The ATI Radeon HD 2900 developed by AMD is a Graphics Processing Unit
(GPU) capable of massively parallel computation for high performance 3D
graphics and general purpose algorithms. The unified shader architecture
consists of a combination of MIMD and SIMD architectures of 5 way scalar
arithmetic units running in parallel. The shader uses multi-threading to
hide latency of memory access so that compute units are keep busy. The
threads consist of vertex, geometry and pixel threads that represent
different programmable stages of a traditional 3D graphics pipeline
mapped onto a single scheduled shader unit. Varied distributed and
unified caches are used for data, instructions, read only texture reads
and vertex data. A ring based memory subsystem allows multiple clients
to access multiple memory channels.
Michael Doggett is a Principal Member of Technical Staff within AMD's
Graphics Product Group. He has worked on the Radeon2900 and previously
the XBOX360 GPU and continues to work on upcomping high end GPUs. He
worked as a Post-Doc at the University of Tuebingen, Germany on
displacement mapping and volume rendering hardware. He has a B.E, B.Sc
and PhD from the University of New South Wales, Sydney, Australia.
16:15-16:30: Best Paper presentation and closing
A PowerPoint
template for presentations is now available.
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